The rapidly growing semiconductor manufacturing sector reported sales nearing $400 billion in 2017, which was a 16% increase over 2015 [1, 2]. High-volume semiconductor device manufacturing requires robust quality control and failure analyses processes. Many failure analysis techniques, both nondestructive and destructive, have been developed in the past five decades [3-6]. A popular technique is device delayering, which is the controlled removal of device layers from the top-down. Information gained through this technique can support quality control and failure analyses efforts, as well as yield product and process improvement data. Focused ion beam (FIB) techniques are often used when delayering semiconductor devices [5, 7, 8]. However, using FIB technology for device delayering has limitations; the most important limitation being the relatively small delayering area: about 20 × 20 μm for Ga FIB [5] and about 100 × 100 μm for Xe FIB [8-10]. That limitation prevents the exposure of a large slope area on the sample, which reveals all layers simultaneously. Tools that yield a small delayering area not only limit characterization, they also limit sample size. For example, FIB-based techniques cannot currently sample multiple regions of interest (ROI) on a whole (unbroken) 300 mm wafer.
展开▼
