Silicon Package Preparation Options for Focused Ion Beam (FIB) Circuit Editing General Packaging Failure Analysis

摘要

The Focused Ion Beam (FIB) technique of internal modification for chip repair, layout verification, and internal signal probe access has become an integral part of the process for bringing advanced products to market. The pervasive switch from wire bond connections to single component flip-chip solder bump mounting on high value products has greatly aided the task of FIB editing by placing the bare backside silicon of the die within easy reach. FIB chip circuit access begins with task-specific sample preparation. The package opening and silicon prep process is well defined and quite robust when full thickness chips are mounted to simple ceramic carriers. Unfortunately, the introduction of flexible organic laminate substrates and the development of stacked die packaging has further complicated the process. Multi-chip packages containing combinations of full thickness and thinned chips may be present. They could be wire-bond connected, or use Through-Silicon Vias (TSV) for double sided attachment. Multiple heat treatment cycles joining together materials with vastly different coefficients of thermal expansion (CTE) may result in severe package warpage and stress. All of these conditions and possible combinations have served to invalidate key elements of the established sample preparation process, and made each presented case unique. As the FIB team works to develop new precision techniques for internal circuitry access, the greater semiconductor packaging development and failure analysis community has benefited from the introduction of new tooling and methodologies.