Integrated Processing of Mega- and Gigabit DRAMs

摘要

The fast pace with which DRAM cell sizes are reduced leads to numerous new challenges in technology development and manufacturing. In addition to the technical challenges of scaling the minimum dimensions below 0.25μm several other problems have to be solved. System requirements for higher bandwidths between memory and processors require faster transistor performance. The cell size for future Gigabit DRAMs approaches a wire pitch limit and thus leads to array devices of minimum dimensions and the challenge to explore new cell architectures. This talk discusses the main integration aspects of deep trench DRAM processes as well as device, cell, and capacitor scaling issues in comparison to stacked DRAM cells for next DRAM generations.