FM/MW Frequency and Clock Lcd Display Driver

摘要

A FM/MW frequency and clock circuit with a 4-digit LCD display driver is presented here. It is a mixed mode design and is used for FM/MW radio frequency display, 12/24 hour clock display with alarm, snooze and sleep function. The input voltage at FM/MW is as low as 300mV and frequency of FM signal can be as high as 150MHz. The supply voltage range for VDD is from 3V to 5.5. The chip is fabricated in 0.7 #mu#m CMOS process. The simulators are Verilog-XL, ST-spice and Eldo.