A 10 bit, 40Ms/s Pipelined A/D Converter

摘要

A low power, 10 bit, 40Ms/s Pipelined Redundant Signed Digit (RSD) Analog to Digital Converter (ADC) is presented. True 10 bit performance with +/- 1/2 lsb differential and integral nonlinearity is achieved by taking advantage of the RSD principle to correct for gain and offset errors, and through the use of fully differential circuitry to improve power supply rejection and reduce errors due to charge injection. The ADC has been fabricated in a 0.5#mu#m BiCMOS process and dissipates 100mW from a 2.7V power supply. This low power consumption is achieved through the use of double sampling in conjunction with a new switched capacitor gain stage to maintain the required sample rate while allowing the internal circuitry to run at a reduced rate.