As device geometry's for high performance CMOS technology scale down to 0.25-#mu# and lower, Shallow Trench Isolation (STI) becomes a necessity offering improved isolation between devices compared with traditional local oxidation of silicon (LOCOS) isolation techniques. In addition, STI provides greater packing density, smaller channel-width encroachment, superior latch-up immunity, and better planarity. The traditional trench isolation process uses plasma etchback. In that method the process is to erode the photoresist and trench oxide simultaneously. However, this complex scheme is not able to provide good global and within die planarity for 0.25-#mu# technology and below. Recently Chemical Mechanical Planarization (CMP) has been used to study and address several essential STI issues using novel slurries. These slurries have shown encouraging properties, such as high oxide removal rates and very low nitride removal rates which corresonds to high oxide to nitride selectivity. This allows the nitride film to be used as a polish stop layer.
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