Viterbi decoder design approaches for audio and video-rate applications using IP soft cores

摘要

This paper presents results from an audio-rate receiver ASIC and a video-rate receiver ASIC based on an identically functioning Viterbi decoder (constraint length 7,rate1/2,3-bit soft decision,48 state traceback depth) yet implemented with different architectures.The video-rate receiver ASIC targeted a 0.5#um#m CMOS process,and the audio-rate receiver ASIC targeteda 0.6#um#m CMOS process.A hot new design conept called intellectual property (IP) was fully utilized here.Using a parameterized IP soft core model of the Viterbi decoder,two innovative architectures were synthesized to yield the same functionality with different physical and speed requirements.Resource sharing the Viterbi decoder resulted in an audio-rate implementation that was 11x less complex than the identically functioning full parallel video-rate implementation.In addition,using pre-verified IP soft cores resulted in a design cycle reduction of 10x.