Parasitic-Aware Automatic Analog CMOS Circuit Design Environment

摘要

In this work, the parasitic-aware design automation of the two-stage op-amp and bulk-driven OTA in 0.13μm are presented using two well-known swarm-optimization algorithms namely, ABC and PSO algorithms. To achieve the parasitic-aware design, we utilized configurable layouts. We also consider process and temperature variations in the automatic layout-level design of the op-amp. The average design time for layout-level design for op-amp using ABC algorithm is only 108 minutes while that for bulk-driven OTA is only 9 minutes. The obtained results reveal that the concept of parasitic-aware design using configurable layouts is an effective tool for designing high-performance analog CMOS circuits.