In Situ Latency Monitoring for Heterogeneous Real-Time Systems

摘要

With the increasing complexity of both application software and the underlying hardware platforms found in current Real-Time Systems (RTSs), static timing analysis methods are struggling to capture the wide variety of delays. In case of real-time control systems, it thus is common practice in industry to measure system latencies over extended periods of time to ensure compliance with predefined control deadlines that specify the maximum permissible delay between the arrival of a sensor value and the transmission of an actuation signal. As such monitoring is commonly implemented using code instrumentation, it not only requires modification of the RTS-under-test, but also is unable to capture delays caused by I/O peripherals or other components that contribute to the end-to-end (i.e., input-to-output) latencies. In this paper, we propose a latency monitoring methodology for current heterogeneous RTSs that combine a fixed-function System-on-Chip (SoC) with configurable FPGA fabric. The proposed extension enables an RTS based on such a Programmable SoC (pSoC) to perform In situ Monitoring (i.e., without software modification or external hardware) of end-to-end latencies including the I/O delays of current interfaces such as Gigabit Ethernet. We present I/O-to-Fabric Redirecting (to tap into the I/O paths of a pSoC-based RTS) combined with a Trigger/Binning Subsystem (to identify sensor/actuation signals and perform online execution of both latency calculation and histogram generation), for which we propose two implementation options. Our experimental evaluation of the software-driven Trigger/Binning Subsystem shows that our proposed methodology is capable of capturing latency variations over extended periods with sub-microsecond accuracy.