An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays

摘要

Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to overall capacitance ratio. A typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk noise on a net, it may not be possible to activate all aggressors logically or simultaneously. Therefore, pattern generation must focus on activating a maximal subset of aggressors switching on or about the same time the victim net switches, while propagating the fault effect to a primary output. This is a well-known problem. In this paper, we present a solution which uses 0-1 Integer Linear Programming (ILP) in conjunction with circuit transformation to model gate delays. A major contribution of this paper is modeling multi-path fault propagation as a linear programming problem. The proposed technique was applied to ISCAS 85 benchmark circuits. Results indicate that percentage of total capacitance that can be switched varies from 20-80%. Patterns generated by this technique are useful for both manufacturing test application as well as signal integrity verification.