Via Configurable Three-Input Lookup-Tables for Structured ASICs

摘要

In this article we study layout and circuit implementations of 3-input lookup table (3-LUT) for via configurable structured ASIC. We present a new 3-LUT circuit and several layout designs. We also propose a method to improve the delay of any logic function with fewer inputs. A 3-LUT, being able to realize all the 256 3-input functions, enables us to synthesize a circuit using both a standard cell synthesizer and an FPGA technology mapper such as FlowMap. Our study shows that circuits synthesized using a standard-cell synthesizer usually achieves better timing than that obtained by FlowMap. Our study further shows that the well-known 3-LUT implemented with multiplexers achieves better timing, area, and power dissipation. Our methodology can be also employed to study look-up tables with more inputs.