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DIGITALLY CONTROLLED DELAY LINE FOR A STRUCTURED ASIC HAVING VIA CONFIGURABLE FABRIC FOR HIGH-SPEED INTERFACE
DIGITALLY CONTROLLED DELAY LINE FOR A STRUCTURED ASIC HAVING VIA CONFIGURABLE FABRIC FOR HIGH-SPEED INTERFACE
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机译:具有可配置面料的结构化ASIC的数字控制延迟线,用于高速接口
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摘要
A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL.
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