RPTSL: A NEW APPROACH OF REDUCING PSEUDORANDOM TEST SEQUENCE LENGTH

摘要

In this paper, based on the built-in selt-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding the worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register (LFSR). By analyzing compact signature the test lengthes for the worst faults can be obtained. Final, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.