A methodology for comparing various neural architectures and implementations is illustrated. The methodology consists of writing the artificial neural network (ANN) equations in a summation form and the applying a tool termed algorithmic timing parameter decomposition (ATPD). ATPD decomposes an algorithm or set of equations into a computation time formula comprising basic system primitives. A particular architecture has a corresponding computational time formula. Similarly, the primitive elements are dependent on the actual hardware realization and thus will change with the processor used in the system. Computation times therefore can be estimated for different parallel architectures. Implementation of a multilayer perceptron is analyzed in several digital signal processor (DSP)-based parallel architectures.
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