首页> 外文会议>Asian Test Symposium >A 15-valued fast test generation for combinational circuits
【24h】

A 15-valued fast test generation for combinational circuits

机译:组合电路的15值快速测试生成

获取原文

摘要

This paper proposes a test generation algorithm which can be applied to practical VLSI circuits. The key idea of the algorithm is to construct a sensitized path from the primary output to the site of the fault. This change of path construction order is very effective especially for the redundant faults, where their fault effects never propagate to any primary output. Whether or not a fault effect propagates can be easily checked by using 15-value logic. In this case, we can save computation time by not processing path sensitization. Another advantage of this approach is that the number of backtracks is greatly reduced by using information on the fault propagation during the path sensitization and line justification processes. This algorithm is implemented in C and is tested with the well-known benchmark circuits. The test results show that the new algorithm is extremely faster than PODEM.
机译:本文提出了一种测试生成算法,其可以应用于实用的VLSI电路。算法的关键思想是将主输出的敏化路径构成到故障的站点。 Path施工顺序的这种变化非常有效,特别是对于冗余故障,它们的故障效应从未传播到任何主要输出。通过使用15值逻辑可以容易地检查故障效果是否传播。在这种情况下,我们可以通过不处理路径敏化来节省计算时间。这种方法的另一个优点是通过在路径敏感和线条公正过程中使用关于故障传播的信息来大大减少回溯的数量。该算法在C中实现,并用众所周知的基准电路测试。测试结果表明,新算法比Podem更快。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号