Assessing the effectiveness of transition fault testing by the test coverage is misleading and can result on lower product quality. In reality, the actual timing of the test for each fault determines if a delay defect of a given size is detected or not. Transition tests that use actual circuit timings to create tests with the tightest possible timing detect more defects and have higher test effectiveness for a given test coverage. This paper validates this assertion using a Statistical Delay Quality Model (SDQM) model to estimate the Statistical Delay Quality Level (SDQL) of several chips. The comparison includes transition tests generated with and without actual circuit timing as a function of the actual timing of the tests for each fault.
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