Advances in cMUT technology accelerated research efforts in the design of driver/receiver front-end integrated circuits (ICs) for transducer arrays. Considering ASIC manufacturing costs and turn-around times, a thorough assessment of the front-end circuit before tape-out is compulsory. For an accurate evaluation, circuit simulations have to be run on a system-level model that includes the post-layout extracted netlist of the IC and an equivalent circuit for the transducers pulse-echo behavior. In this paper, we present the modeling, design and test of a front-end IC for 2D cMUT arrays. To evaluate the circuit response, we first developed a pulse-echo model for an array element. The model is a modified version of the Mason Equivalent Circuit where the radiation impedance term has been replaced by an RLC network to include the effects of finite transducer size and diffraction loss. The model has been verified by running transient FEA simulations using ANSYS. Meanwhile, we designed a driver/receiver front-end circuit for a 2D cMUT array element. The circuit was composed of a high voltage (50 Volt) pulse driver, an NMOS protection switch and a trans-impedance amplifier. We then used the transducer model to simulate the response of the front-end circuit using Cadence Spectre. The simulation results are then verified by comparing them to experimental data obtained from the manufactured front-end IC. We demonstrated that information obtained from a model describing the behavior of the front-end circuit together with the transducer element is consistent with the experimental data and hence can be used to asses system performance.
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