Test time of multiplier/accumulator based output response analyzer in built-in analog functional testing

摘要

A Built-In Self-Test (BIST) approach has been proposed for functionality measurements of analog circuitry in mixed-signal systems. The BIST circuitry consists of a direct digital synthesizer (DDS) based test pattern generator (TPG) and multiplier/accumulator (MAC) based output response analyzer (ORA). In this paper we investigate and discuss the test time required by the ORA for analog measurements such as frequency response and 3rd order intercept point (IP3). We show that the test time can be greatly shortened if the ORA accumulation can be stopped at the right point. Three simple digital circuits are also proposed for such a purpose and their performance is simulated to show how the efficiency of the test time is improved.