An FPGA based Digital Speech Processor for Auditory Prosthesis

摘要

An FPGA based Digital speech processor system utilizes digital signal processing has been developed for hearing(auditory) prosthesis. The system implements 8 channel of processing and stimulation using continuous interleaved sampling(CIS)strategy. This speech processing system incorporates Xilinx Spartan3 FPGA as the main chip for DSP IP cores, 256kB of FLASH memory, 2kB of EEPROM memory, a 16-bit analog to Digital converter, gain amplifier and transmitter. The transmitter conveys control codes to the receiver stimulator developed in the laboratory as a prototype for testing the performance of the speech processor. The performance details are enumerated with sample experimental results.