Power consumption has become an important issue in the design of high-performance microprocessors. Pipeline activity in superscalar processors represents one of the most significant sources of power dissipation, due to the growing complexity of the out-of-order issue logic and the extra-work caused by speculative execution. Therefore, analyzing speculative techniques from a power-perspective seems to be essential for the design of power-efficient superscalar processors. Value prediction is one of the most recent techniques for increasing ILP through speculative execution. Although it has been proved to be an effective technique for improving performance, its hardware cost and power dissipation can represent two main limitations. The aim of this paper is to explore the main sources of power dissipation to be considered when value prediction is used, and to propose solutions to reduce this dissipation.
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