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Power-sensitive multithreaded architecture

机译:功率敏感的多线程架构

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The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-conscious design must therefore go beyond technology and low-level design, but also change the way modern processors are architected. A multithreading processor is attractive in the context of low-power or power-constrained devices for many of the same reasons that enable its high throughput. Primarily, it supplies extra parallelism via multiple threads, allowing the processor to rely much less heavily on speculation. We show that a simultaneous multithreading processor utilizes up to 22% less energy per instruction than a single-threaded architecture. We also explore other power optimizations that are particular to multithreaded architectures, either because they are unavailable to or unreasonable for single-thread architectures.
机译:微处理器的功耗在设计决策中变得越来越重要,不仅在移动处理器中,而且在高性能处理器中也变得越来越重要。因此,功能意识的设计必须超越技术和低级设计,而且还改变了现代处理器的架构方式。多线程处理器在低功耗或功率约束设备的上下文中具有吸引力,其中许多具有高吞吐量的许多相同的原因。主要是,它通过多个线程提供额外的并行性,允许处理器依赖于猜测。我们表明,同时多线程处理器利用比单线程架构的每条指令少22%。我们还探讨了多线程架构的其他功率优化,因为它们对于单线程架构不可用或不合理。

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