An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction awaits the result of a prior instruction. The architecture coordinates the processing of data for multiple instructions through a multiple stage data pipeline. As a result, the architecture not only supports simultaneous execution of multiple programs, but also permits each program to execute without delays caused by inter-relationships between instructions within the program. A memory update engine provides flexible modification of data in memory. A processor may employ the update engine to update filter coefficients, special effects parameters, signal sample processing instructions, or any other instruction or data during processing. The update engine supports dynamic updating without requiring processor shutdown, thereby allowing the processor to seamlessly continue operation during a live performance.
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