Advanced wiring RC timing design techniques for logic LSIs in gigahertz era and beyond

摘要

In this paper, we describe an advanced wiring RC timing design techniques for the gigahertz era. Our new technique of wiring capacitance extraction makes it possible to calculate more than 1 M nets within 3 hours as accurately as carrying out net-by-net 3-D simulations. Furthermore, we introduced the timing window for estimating crosstalk effects on delay time so as to distinguish harmful nets from harmless nets and reduce surplus design guard-bands.