Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz

摘要

This paper presents a cell-based 50% Duty-Cycle Correction (DCC) design supporting a super-wide range of clock frequency from 10MHz to 1.2GHz, using a 90nm CMOS process. It can be integrated with a Delay-Locked Loop (DLL) as a convenient post-processing unit while achieving “zero phase shift” in a way that the phase locking result achieved by its precedent DLL is not affected at all. The unique features in this design include: (1) A wide-range and high-resolution Half-Period Tunable Delay Line (HP-TLD), (2) A fast-locking unit to enable our DCC to lock in to a new incoming clock frequency during frequency scaling, and (3) A wide-range and high-resolution Duty-Cycle Judge (DCJ) circuit as a feedback to guide the overall duty-cycle correction process. Post-layout simulation in a 90nm CMOS process is conducted to validate its effectiveness.