In this paper, the effect of process variations on the delay of CMOS static logic circuits is discussed versus fan-in. In particular, the effect of process variations in stacked transistors (which determine the fan-in) is analytically evaluated. From circuit analysis, a simple analytical model is derived that expresses the delay variation as a function of the number of stacked transistors and transistor size. Theoretical results are useful to gain an insight into the dependence of the delay variation on design parameters. Monte Carlo simulations on a 90-nm technology were performed to validate the results.
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