Reducing operating voltage from 3, 2, to 1 volt andbelow-challenges and guidelines for possible solutions CMOS

摘要

We discuss challenges to reducing integrated circuit powerconsumption by reducing operating voltage, and guidelines for possiblesolutions via processing technology and circuit design. Migrating from3-Volt to 2-Volt operation, the key issue is optimizing the processingtechnology to maintain the performance. At 1 Volt, interfacinglow-voltage circuits with standard I/O becomes the main challenge. To gobelow 1 Volt, we must re-visit transistor design issues very carefully