Fully planarized four-level interconnection with stacked vias usingCMP of selective CVD-Al and insulator and its application to quartermicron gate array LSIs

摘要

The chemical mechanical polishing (CMP) of selective aluminum (Al)CVD via plugs is examined for the first time and a fully planarizedfour-level interconnection system with all stacked via plugs isdemonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plughas proved to be one of the best via plug structures because of its lowvia resistance and extremely high reliability. Quarter-micron 120-kGgate array LSIs have been successfully fabricated using a 1.4 μm,equal pitch, four-level interconnection