Deriving Efficient Area and Delay Estimates by Modeling Layout Tools

摘要

This paper presents a novel approach to deriving area and delay estimates for high level synthesis using machine learning techniques to model layout tools. This approach captures the relationships between general design features (e.g., topology, connectivity, common input, and common output) and layout concepts (e.g., relative placement). Experimentation illustrates the effectiveness of this approach for a variety of real-world designs.