This paper describes algorithms for automatic layout synthesis of leaf cells in 1-d and in a new 1-1/2-d layout style, useful for non-dual circuit styles. The graph theory based algorithms use concepts set forth by Euler and Hamilton to achieve two tasks. The transistor placement algorithm uses the Euler's theorem, while the placement of the groups of the transistors is achieved by using Hamiltonian graphs. Results show that the algorithms produce extremely competent layouts when compared to other algorithms in the literature and manual layouts.
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