We address the problem of verification and testing of super scalarprocessors, from the point of view of correctness of [Bprogram executiontime. Trace-driven architectural si[Bmulation methods are commonly usedin current industrial practice to estimate cycles-per-instructionperformance of a candidate processor organization, prior to actualimplementation. We present a novel set of strategies for testing thetiming correctness of processors as represented in an architecturaltiming model (“timer”). We focus on two main aspects of thetheory: (a) deriving architectural test sequences to cover possiblefailure modes, defined in the context of a pipeline flow statetransition fault model; and (b) deriving loop test kernels to verifysteady-state (periodic) behavior of pipeline flow, against analyticallypredicted signatures. We develop the theory in the context of an examplesuper scalar processor and its timer model
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