Test pattern generation for path delay faults in synchronoussequential circuits using multiple fast clocks and multiple observationtimes

摘要

The problem of test generation for path delay faults insynchronous sequential circuits is addressed. In existing testingmethods, a single fast clock cycle is used to activate path delay faultsand a fault is said to be detected only if the fault free response isdifferent from the faulty response at a single output and at a specifiedtime unit in the test sequence. We refer to these methods as single fastclock cycle and single observation time testing methods. We show thattestable faults may exist, which are untestable using a single fastclock cycle and a single observation time. Such faults are testable whenmultiple fast clock cycles and/or multiple observation times are used. Atest generation procedure is given that uses multiple fast clock cyclesand multiple observation times. Experimental results are presented onMCNC synthesis benchmarks to demonstrate the effectiveness of theproposed strategy in increasing the fault coverage and reducing the testlength