首页> 外文会议>Electron Devices Meeting, 2000. IEDM Technical Digest. International >Three dimensional CMOS integrated circuits on large grainpolysilicon films
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Three dimensional CMOS integrated circuits on large grainpolysilicon films

机译:大晶粒上的三维CMOS集成电路多晶硅膜

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In this paper, we report high performance three-dimensional (3-D)CMOS integrated circuits. The first layer of transistors is fabricatedon Silicon-on-Insulator (SOI) and second layer is fabricated onlarge-grain polysilicon-on-insulator (LPSOI) film, with oxide as theinterlayer dielectric. The LPSOI film is formed by there-crystallization of amorphous silicon through metal-induced lateralcrystallization (MILC) at an elevated temperature. Compared with theconventional 2-D CMOS SOI low-voltage circuit, 3D circuit showssignificant reduction in circuit area, shorter propagation delay andlower dynamic power consumption
机译:在本文中,我们报告了高性能三维(3-D) CMOS集成电路。制造第一层晶体管 在绝缘体上(SOI)和第二层进行制造 大谷多晶硅on绝缘体(LPSOI)薄膜,氧化物为 层间电介质。 LPSOI薄膜由此形成 通过金属诱导的横向重新结晶非晶硅 在升高的温度下结晶(MILC)。与之相比 传统的2-D CMOS SOI低压电路,3D电路显示 电路面积显着降低,传播延迟较短 降低动态功耗

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