A Spice-compatible flash EEPROM model feasible for transient andprogram/erase cycling endurance simulation

摘要

A complete Spice-compatible model for stacked-gate flash EEPROMcells has been successfully developed. It includes an accurate DC I-Vmodel, a gate current model for Channel Hot Electron (CHE) programming;and a channel Fowler-Nordheim (FN) current model for erase. Program anderase induced oxide damage are also included in the model. For the firsttime, it allows the simulation of the programming/erase transient andthe P/E cycling endurance characteristics using the present analyticalapproach. It provides an easy way for applications to cell designoptimization and reliability evaluation for device and circuit designers