Novel 0.44 μm2 Ti-salicide STI cell technology forhigh-density NOR flash memories and high performance embeddedapplication

摘要

This paper describes the key technology to realize high densityflash memory, which has quarter-micron Shallow Trench Isolation (STI),Ti-silicided polycrystalline silicon (poly-Si) gate and source/drain,and tungsten (W) local inter-connect sourceline. Extremely small cellsize of 0.44 μm2 has been obtained with 0.25 μm designrule. This cell size is about 30% that of conventional NOR flash cell.To minimize the cell size, the cell gate is patterned with length of0.25 μm, which can be achieved by using channel erasing scheme. STIand 0.15 μm floating gate separation can realize a 0.55 μm bitlinepitch. W sourceline can reduce sourceline resistance and the number ofmetal sourcelines in the array. In addition, poly-Si gate and activesource/drain areas are Ti-silicided at both cells and peripheraltransistors, which results in high-speed operation of memory array andperipheral circuits. This high-density NOR cell technology will beessential to realize a low cost and high-performance flash memory andflash embedded logic devices