Transient reverse voltage ratings for very high voltage silicon devices are usually established with the aim of maintaining the applied voltage below the avalanche breakdown voltage of the device. This approach is used because many p-n junction devices have surface limited reverse voltage characteristics. Unfortunately, the transient energy which can be dissipated during surface breakdown is both unpredictable and significantly lower than that which can be absorbed within the body of the device. By suitable design high voltage p-n junction device can be constructed with the electric field at the junction surface reduced sufficiently such that the avalanche region is confined to the body of the device.
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