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Time Delay Control Methodology for High Speed Substrate Design

机译:高速基板设计的时延控制方法

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摘要

For the high speed substrate design, the synchronization of the signals is one of the most important concerns. Time delay control methodologies that are based on high speed substrate design rules which include equalizing differences between the same group high speed transmission lines, maximizing time balance between different high speed transmission lines and balancing over all nets difference between every high speed transmission lines. In this paper, we consider approaches that include ground trace impacts, near by differential pairs, and reference ground plane edging to minimize the time delay between traveling signals through different high speed propagation paths. We also propose the design guidelines to minimize the time delay of signal paths. The rules are applied to high speed differential pair design FCBGA, and the time delay is controlled within 3 pico seconds.
机译:对于高速基板设计,信号的同步是最重要的问题之一。基于高速基板设计规则的时延控制方法,包括均衡同一组高速传输线之间的差异,最大化不同高速传输线之间的时间平衡以及平衡每条高速传输线之间的所有网络差异。在本文中,我们考虑了包括接地迹线影响,差分对附近的影响以及参考接地平面边缘的方法,以最小化通过不同的高速传播路径传播信号之间的时间延迟。我们还提出了设计准则,以最大程度地减少信号路径的时间延迟。该规则适用于高速差分对设计FCBGA,并且时间延迟控制在3皮秒内。

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