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QC-LDPC Codes with Fast Encoding for Error Control in NAND Flash Memories

机译:快速编码的QC-LDPC码用于NAND闪存中的错误控制

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In this paper we show the construction procedure for QC-LDPC codes with low encoding complexity and structure optimized for hard decision decoding and low precision soft decoding, which both are involved in a modern error correction control for NAND flash memories. The procedure is based on a computer search for codes with linear encodability, while error correction performance is optimized by reducing the number of weight-2 columns in the parity check matrix and optimizing structure of the code graph, particularly eliminating short cycles. We also show a simple method for code rate adjustment by extending the parity check matrix altogether with codeword shortening to enable more robust error correction when raw error rate of memory cells increases with the memory lifetime. The approach is validated via error rate Monte Carlo simulations with hard decisions and low precision soft decisions LDPC decoding, with a flash memory cell error model.
机译:在本文中,我们展示了具有低编码复杂度的QC-LDPC码的构造过程,以及针对硬判决解码和低精度软解码进行了优化的QC-LDPC码的构建过程,它们都涉及NAND闪存的现代纠错控制。该程序基于计算机对具有线性可编码性的代码的搜索,同时通过减少奇偶校验矩阵中的weight-2列数和优化代码图的结构来优化纠错性能,尤其是消除了短周期。我们还展示了一种简单的方法,可通过将奇偶校验矩阵与代码字缩短一起扩展来扩展奇偶校验矩阵,从而在存储单元的原始错误率随着存储寿命而增加时实现更强大的错误纠正。该方法通过具有硬判决和低精度软判决LDPC解码的误码率Monte Carlo仿真以及闪存单元错误模型进行了验证。

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