A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications

摘要

We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at given leakage over 14LPP with comparable reliability and yield. In addition, SRAMs benefit from a 30% leakage reduction at the same Iread. 12LP extends the 14nm technology with compelling performance and area scaling.