Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique

摘要

Circuits designed for space applications need specialconsideration to tolerate radiations. Guarded dual modularredundancy (GDMR), a radiation hardened by design (RHBD)technique for single event transients (SETs) is presented in thispaper. We present a neat mathematical procedure that capturesthe effects of multiple event transients (METs) in any givenradiation-hard by design (RHBD) technique. We analyze the effectiveness of GDMR multiple event transients (METs) againstthe well-known triple-modular redundancy (TMR) techniqueusing this procedure. Our results show that GDMR logic gatesexhibit far better tolerance to METs as compared to TMR gates,except for some logic gates. We have implemented several logicgates and a benchmark circuit (C17) using unhardened, GDMRand TMR techniques in UMC 65nm technology and comparedthem. Our simulations of various logic gates show that GDMRgates consume about 50% less power, 3x less area, and about 50% less delay compared to their TMR counterparts, and yet, GDMR outperforms TMR in terms of error-tolerance to METs by about 3x, except for some gates. For C17 ISCAS-85 Benchmark circuit implemented in UMC 65nm, we find that GDMR implementation consumes about 58% less area, has 31% less delay, 19% less power and 32% less probability of error due to METs than TMR implementation.