Real-time implementation of Fractal Image Compression in low cost FPGA

摘要

Fractal Image Compression (FIC) is one of the most popular techniques used in image and video compression due to its simplicity and superior performance. The main drawback of FIC arises from its time consuming operation, especially when a full search is attempted. Hence, it is very challenging to achieve a real-time operation if this algorithm is implemented in general processor unit. In this paper, a new parallel architecture is proposed for implementing a full-search FIC coding. This proposed design is synthesized on a low-cost FPGA and optimized at circuit level in order to achieve a near real-time operation. The performance of the proposed architecture is quantitatively evaluated in terms of run-time, peak-signal-to-noise-ratio (PSNR) and compression efficiency. A run-time equivalent to a video speed of 20 frame per second (fps) is easily achieved on this new hardware with PSNR and compression ratio averaging at 30 dB and 5.82 % respectively.