R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS

摘要

This paper presents a design approach for upgrading the resiliency of ultra-low-voltage (ULV) microprocessors through a voltage-scalable and low-overhead in-situ error detection and correction (EDAC) technique. Particular efforts are made to overcome the poor voltage scalability and area/energy/throughput overhead of the existing EDAC techniques when applied to ULV designs. The 0.4V, 16b microprocessor employing the proposed EDAC and dynamic frequency scaling schemes is demonstrated in 65nm. The microprocessor can (1) automatically modulate fCLK based on error flags across static/slow variations and (2) in-situ detect and correct the errors from fast dynamic variations, virtually eliminating timing margins. At a typical process/voltage/temperature (PVT) corner, the proposed design achieves 4.9× throughput and 59% energy efficiency improvement at only 9.5% area overhead over the baseline design under the worst-case timing margin.