A 4.4#x2013;5.4GHz digital fractional-N PLL using #x0394;#x03A3; frequency-to-digital converter

摘要

A phase interpolator (PI) based fractional divider is used to improve the quantization noise shaping properties of a 1-bit ΔΣ frequency-to-digital converter (FDC). Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed FDC in place of a high resolution TDC and achieves −102dBc/Hz in-band phase noise and 852fsrms integrated jitter (1k–40M) while generating 5.054GHz output from 31.25MHz input.