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Design of High-Speed Mixed-Signal Circuits in 65 nm and 28 nm CMOS Technology for Optical Transmitters with Data Rates beyond 100 Gbit/s per

机译:65 nm和28 nm CMOS技术的高速混合信号电路设计,用于数据传输速率超过每秒100 Gbit / s的光发射器

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High-speed DACs that have sufficient resolution as well as application specific digital signal processors (DSP) are key components for optical transmitter modules that support data rates beyond 100 Gbit/s per optical wavelength channel. To reach such large data rates higher order modulation formats (i.e. n-fold QAM) have to be applied. The high order modulation can be combined with multi tone techniques (i.e. OFDM) to optimally use the available optical bandwidth. Advanced CMOS technologies allow for the integration of the digital signal processor on a single ASIC as ??System-on-Chip?? (SoC). Thus the optical transmitter may be implemented in a compact and cost-efficient way. The DACs and their interface to the DSP are designed as full-custom mixed-signal integrated circuits with extensive analog circuitry. The DSP may be implemented in a semi-automated way based on VHDL/Verilog and a standard cell library. This paper presents the design of an optical OFDM Tx IC in 65 nm CMOS technology. The IC supports data rates far beyond 100 Gbit/s per optical wavelength channel and the optimal use of the available SNR in the OFDM subchannels by means of two 32 GS/s 8 bit DACs and a standard-cell based DSP. Further the design of a 100 GS/s 8 bit DAC in 28 nm CMOS technology is presented. The DAC features an integrated memory to output cyclical symbol sequences and a hardware prototype of the DAC is already available.
机译:具有足够分辨率的高速DAC和专用数字信号处理器(DSP)是光发射器模块的关键组件,这些模块支持每个光波长通道超过100 Gbit / s的数据速率。为了达到如此大的数据速率,必须采用更高阶的调制格式(即,n倍QAM)。高阶调制可以与多音调技术(即,OFDM)结合以最优地使用可用的光带宽。先进的CMOS技术可将数字信号处理器集成在单个ASIC上,称为“片上系统”。 (SoC)。因此,可以以紧凑且成本有效的方式来实现光发射器。 DAC及其与DSP的接口被设计为具有广泛模拟电路的全定制混合信号集成电路。可以基于VHDL / Verilog和标准单元库以半自动方式实现DSP。本文介绍了采用65 nm CMOS技术的光学OFDM Tx IC的设计。该IC通过两个32 GS / s 8位DAC和一个基于标准单元的DSP,支持每个光波长通道远超过100 Gbit / s的数据速率以及OFDM子通道中可用SNR的最佳利用。进一步介绍了采用28 nm CMOS技术的100 GS / s 8位DAC的设计。 DAC具有集成存储器以输出循环符号序列,并且DAC的硬件原型已经可用。

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