A low-hardware consumption FPGA based configurable LDPC decoder

摘要

FPGAs are widely used for evaluating the performance of low-density parity check (LDPC) codes. But most of the existing LDPC decoders are designed for structured codes and extremely resource consuming. In this paper we propose a low-consumption configurable decoder architecture and a universal mapping algorithm for extrinsic messages to cope with structured or random regular LDPC codes. It can be implemented in low-priced products such as XILINX Spartan FPGAs family. In comparison with the decoders previously implemented, the proposed decoder significantly reduces the number of block RAMs used for extrinsic messages with no loss of throughput.