Secure systolic Montgomery modular multiplier resilient to Hardware Trojan and Fault-Injection attacks

摘要

During the Montgomery modular multiplication over prime fields, the linear arithmetic code check part of immediate result of each step can be calculated by those of the input parameters and an immediate state. Based on this theory, a novel secure architecture of secure systolic Montgomery modular multiplier resilient to Hardware Trojan and Fault-Injection attacks is proposed. The proposed architecture has been verified by modeling it using VHDL, implementing and testing it on Xilinx Virtex-4 FPGA. The multi-bit error detection capabilities are more than 96.9% if the errors stay for only one cycle, or nearly 99% if the errors stay for multiple cycles; the hardware overhead is about 20.99% and time overhead is zero.