Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCs

摘要

This paper demonstrates an electronic design automation (EDA) tool flow for generation of digitally controlled high-bandwidth on-chip voltage regulators for easy integration in a digital SoC. The proposed flow optimizes the control loop and power stage of an integrated voltage regulator (IVR) to achieve desired transient performance and/or efficiency. The GDSII of the optimized IVR is generated by coupling logic synthesis and physical design of digital blocks, automated generation of power stage layout, and top-level integration of all modules. We demonstrate the developed flow for inductive IVRs in 130nm and 65nm CMOS process. We show feasibility of fast design space exploration, optimization, layout generation as well as automated integration of the generated IVR with a RISC-V core.