A second-order anti-aliasing prefilter for an SDR receiver

机译：SDR接收器的二阶抗混叠前置滤波器

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A new architecture is presented for a sinc/sup 2/(f) filter intended to sample channels of varying bandwidth when surrounded by blockers and adjacent bands. Sample rate is programmable from 5 to 40 MHz, and aliases are suppressed by 45 dB or more. The 0.13-/spl mu/m CMOS circuit consumes 6mA from 1.2V.

机译：提出了一种用于Sinc / sup 2 /（f）滤波器的新架构，该滤波器旨在在被阻塞器和相邻频带包围时对带宽变化的信道进行采样。采样率的可编程范围是5至40 MHz，混叠抑制了45 dB或更多。 0.13- / spl mu / m CMOS电路从1.2V消耗6mA的电流。

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《Custom Integrated Circuits Conference, 2005 IEEE》|2005年|P.629-632|共4页
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Mirzaei; A.; Bagheri; R.; Chehrazi; S.; Abidi; A.A.;
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中图分类工业技术;
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CMOS integrated circuits; VHF filters; antialiasing; channel bank filters; radio receivers; software radio; 0.13 micron; 1.2 V; 5 to 40 MHz; 6 mA; CMOS circuit; SDR receiver; adjacent bands; anti-aliasing prefilter; blockers; second-order prefilter;

机译：CMOS集成电路; VHF滤波器;抗混叠;通道组滤波器;无线电接收器;软件无线电; 0.13微米; 1.2 V; 5至40 MHz; 6 mA; CMOS电路; SDR接收器;相邻频带;抗混叠预滤波器;阻挡器;秒阶预过滤器;

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2. A 0.5 mm$^{2}$ Power-Scalable 0.5–3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler [J] . Geis A., Ryckaert J., Bos L., Solid-State Circuits, IEEE Journal of . 2010,第11期

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3. New SDR Receiver SDR-4 Receiver [J] . Radiouser . 2011,第11期

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4. A second-order anti-aliasing prefilter for an SDR receiver [C] . Mirzaei, A., Bagheri, Custom Integrated Circuits Conference, 2005 IEEE . 2005

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A second-order anti-aliasing prefilter for an SDR receiver

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