The introduction of low-priced test systems and the reduction ofthe test time are necessary in order to decrease the testing costs thatare included in the cost of manufacturing VLSI. However, coupled withthe miniaturization of the fabrication process, the test time tends tobecome considerably longer for multifunctional and complex VLSI withhigh integration. In this paper, we present a new method enabling theautomatic reduction of the test time. This method consists of shorteningthe test time by installing virtual tester hardware on the tester CPUmemory in order to delete duplicate tester hardware settinginstructions. The efficiency of this method is proven by experimentsshowing that a test time reduction of 5~25% could be obtained
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