The approach to multiple instruction execution in the GMICRO/400processor

摘要

This paper describes the instruction execution mechanism of the32-bit microprocessor GMICRO/400 that executes more than one operationper clock cycle. The chip integrates a dual operation integer unit, afloating-point unit, an 8-Kbyte instruction cache, an 8-Kbyte datacache, and a 64-bit external data bus. The GMICRO/400 utilizes bothsuperscalar and VLIW design techniques. The integer unit and thefloating-point unit concurrently execute two integer and onefloating-point instructions. The dual operation integer unit executestwo operations in one clock cycle, under the control of a microprogramusing long microinstruction words, when it executes a multiple-operationinstruction