VLSI architecture for motion estimation using the block-matchingalgorithm

摘要

In this paper an architecture is described that implements motionestimation in image coding, using a block-matching algorithm and anexhaustive search method. The architecture, EST256, consists of 256processor elements, deals with a search area of -8/+7 and performs 11GOPS (subtraction, absolute value determination, accumulation andcomparison). It is implemented with ES2 0.7 μm double-metal-layerCMOS technology. This ASIC is cascadable to deal with bigger searchareas